상세정보
학술지
Distributed memory access architecture and control for fully disaggregated datacenter network
- 발행일
- 202212
- 출처
- ETRI Journal, v.44 no.6, pp.1020-1033
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 21HH5900, [전문연구실/통합과제] 광 클라우드 네트워킹 핵심기술 개발 , 이준기
- 초록
- In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1혻μs. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 μs. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 μs for all MI traffic with less than 10% of transmission overhead.
- KSP 제안 키워드
- Average memory access time, CPU-intensive, Control scheme, Data Center Networks, Distributed scheduler, Hardware Implementation, Priority-Based, Round trip time, Scheduling algorithm, access control, delay-sensitive
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