상세정보
학술지
Power Limiter with PIN Diode Embedded in Cavity to Minimize Parasitic Inductance
- 발행일
- 202211
- 출처
- Journal of Electromagnetic Engineering and Science, v.22 no.6, pp.686-688
- ISSN
- 2671-7255
- 출판사
- 한국전자파학회 (KIEES)
- 협약과제
- 21IU1200, 국방 무기체계용 핵심 반도체 부품 자립화 플랫폼 개발, 임종원
- 초록
- This letter introduces a power limiter that limits the input power to protect the receiver when a large power enters the radio frequency receiver. When the power limiter receives a large power signal, a positive-intrinsic-negative (PIN) diode is turned on to limit the input power by lowering the impedance. We analyzed the characteristics of the power limiter according to the method of connecting the PIN diode in parallel with the input and output transmission lines of the power limiter. By embedding a PIN diode into the cavity and minimizing the length of the wire, a power limiter was designed and implemented to minimize parasitic inductance. In the S-band, the proposed power limiter's insertion loss was below 0.5 dB, and the reflection loss characteristics were below 15 dB. Furthermore, it achieved an output P1dB of 21.8 dBm at 3.5 GHz.
- KSP 제안 키워드
- 3.5 GHz, Input power, Loss characteristics, PIN Diode, Parasitic inductance, Power Signal, Power limiter, Radio Frequency(RF), S-Band, Transmission line, input and output
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