$^{\circ}$ /180 $^{\circ}$ with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P $_{\mathrm{1\,dB}}$ was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%." /> $^{\circ}$ /180 $^{\circ}$ with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P $_{\mathrm{1\,dB}}$ was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%." />

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Journal Article Three-Stacked CMOS Power Amplifier to Increase Output Power With Stability Enhancement for mm-Wave Beamforming Systems
Cited 15 time in scopus Share share facebook twitter linkedin kakaostory
Authors
Hayeon Jeong, Hui Dong Lee, Bonghyuk Park, Seunghyun Jang, Sunwoo Kong, Changkun Park
Issue Date
2023-06
Citation
IEEE Transactions on Microwave Theory and Techniques, v.71, no.6, pp.2450-2464
ISSN
0018-9480
Publisher
IEEE
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1109/TMTT.2022.3228539
Abstract
In this study, an mm-wave band complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a two-stage differential structure was designed. An analysis of the designed PA is presented and a new structure is proposed to eliminate the possibility of oscillation in the PA, which has high gain and high output power. The designed driver stage consists of a pair of cascode amplifiers and can be advantageously applied in beamforming systems as the PA phase is converted to 0 $^{\circ}$ /180 $^{\circ}$ with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P $_{\mathrm{1\,dB}}$ was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%.
KSP Keywords
3 V, As 2, Bias voltage, CMOS Process, CMOS power amplifier, Differential structure, High Gain, Peak power, Power added efficiency(PAE), Power stage, RF CMOS
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