상세정보
학술지
Tensor slicing and optimization for multicore NPUs
- 발행일
- 202305
- 출처
- Journal of Parallel and Distributed Computing, v.175, pp.66-79
- ISSN
- 0743-7315
- 출판사
- Elsevier
- 협약과제
- 22HS2300, 인공지능 시스템을 위한 뉴로모픽 컴퓨팅 SW 플랫폼 기술 개발, 김태호
- 초록
- Although code generation for Convolution Neural Network (CNN) models has been extensively studied, performing efficient data slicing and parallelization for highly-constrained Multicore Neural Processor Units (NPUs) is still a challenging problem. Given the size of convolutions' input/output tensors and the small footprint of NPU on-chip memories, minimizing memory transactions while maximizing parallelism and MAC utilization are central to any effective solution. This paper proposes a TensorFlow XLA/LLVM compiler optimization pass for Multicore NPUs, called Tensor Slicing Optimization (TSO), which: (a) maximizes convolution parallelism and memory usage across NPU cores; and (b) reduces data transfers between host and NPU on-chip memories by using DRAM memory burst time estimates to guide tensor slicing. To evaluate the proposed approach, a set of experiments was performed using the NeuroMorphic Processor (NMP), a multicore NPU containing 32 RISC-V cores extended with novel CNN instructions. Experimental results show that TSO is capable of identifying the best tensor slicing that minimizes execution time for a set of CNN models. Speed-ups of up to 21.7% result when comparing the TSO burst-based technique to a no-burst data slicing approach. To validate the generality of the TSO approach, the algorithm was also ported to the Glow Machine Learning framework. The performance of the models were measured on both Glow and TensorFlow XLA/LLVM compilers, revealing similar results.
- 키워드
- Burst-based cost model, Convolutional neural network, Mapping strategies, NPU
- KSP 제안 키워드
- Burst Time, Burst data, Convolution neural network(CNN), Data transfer, LLVM compiler, Learning framework, Mapping strategies, Neural processor, On-chip, RISC-V, code generation