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Conference Paper
Chiplet Heterogeneous-Integration AI Processor
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- Authors
- Youngsu Kwon, Jinho Han, Yongcheol Peter Cho, Juyeob Kim, Jaehoon Chung, Jaewoong Choi, Sujin Park, Igyeong Kim, Hyunjeong kwon, Jinkyu Kim, Hyunmi Kim, Won Jeon, Youngdeuk Jeon, Minhyung Cho, Minseok Choi
- Issue Date
- 2023-02
- Citation
- International Conference on Electronics, Information and Communication (ICEIC) 2023, pp.1-2
- Language
- English
- Type
- Conference Paper
- Abstract
- The scale of neural networks for Artificial Intelligence is ever increasing to achieve human-level intelligence. The era of data explosion computing is evolving with the advent of the huge AI network operating on huge amount of data including parameters, images, sentences, and etc. Designing AI processor which is the computational foundation of the data explosion computing is facing physical limitation of semiconductors as well as skyrocketing cost. The chiplet processor integrating multiple dies into a single chip is a viable solution to deal with AI processors for data explosion computing. The chiplet-based design compared to IP-based design provides much higher performance with lower cost. In this paper, we present design aspects of chiplet AI processor including the architecture design for incorporating NPU chiplets, HBM chiplets, and 2.5D interposers, signal integrity for high-speed interconnections on the interposer, PDN for chiplets, chiplet-bonding reliability, thermal stability, and chiplet link for inter-chiplet data transfer on heterogeneous integration architecture.
- KSP Keywords
- 2.5D interposers, Architecture Design, Data explosion, Data transfer, Design Aspects, High Speed, Higher performance, IP-Based, Integration architecture, Lower cost, Signal Integrity(SI)