상세정보
학술대회
Computationally Efficient Coherent Correlator Design for DVB-S2 Receiver
- 발행일
- 201008
- 출처
- International Conference on Electronics and Information Engineering (ICEIE) 2010, pp.V2-58-V2-62
- 협약과제
- 10MR1700, 통해기위성 Ka대역 통신탑재체 우주인증 및 실용화 검증기술 개발, 안도섭
- 초록
- Computational complexity of a coherent correlator is dominated by the number of complex multiplications and additions involved in process. In this paper a unique multiplier-less approach of coherent correlation has been proposed for Digital Video Broadcasting Second Generation (DVB-S2) receiver. It can be used in high speed communication of DVB-S2 because of its simplified architecture. The proposed design shows a huge amount of hardware saving as well as it improves the processing speed of the correlator over the conventional approach. It is also advantageous in terms of On-chip memory requirement. The functionality of the design has been verified through simulation and synthesis of the existing and proposed correlation scheme. The proposed architecture is optimized in terms of area with 97% reduction in number of LUTs. The critical speed of design on Virtex4 FPGA is 1364 MHz and it consumes 1.29W power which is 9.28% of the power consumed by conventional architectures. The proposed coherent correlator architecture can be used with the Data Aided (DA) receiver schemes (such as Frame synchronization, SNR estimation) used in the DVB-S2 standard. © 2010 IEEE.
- KSP 제안 키워드
- Computational complexity, Computationally Efficient, DVB-S2, Digital video broadcasting, Frame synchronization, High Speed Communication, Processing speed, SNR Estimation, Second generation(2G), critical speed, multiplier-less