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An Efficient AER Interface Circuit for Scalable Spiking Neural Networks
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- Authors
- Sung-Eun KIm, Kwang-Il Oh, Taewook Kang, Sukho Lee, Hyuk Kim, Mi-Jeong Park, Jae-Jin Lee
- Issue Date
- 2023-06
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2023, pp.766-768
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- To achieve larger and deeper Spiking neural networks (SNNs) with high energy efficiency, an asynchronous interface circuit for inter-chip communication is essential. However, from the perspective of implementation, there are challenging issues like time latency, throughput and power consumption. In this paper, an asynchronous interface based on address-event-representation (AER) protocol was designed and integrated with a full-custom approach in 28-nm FDSOI process. With an intermediate latching scheme, the proposed interface circuit enabled a multi-pipeline processing and significantly reduced the time latency for spike transmission between layers of SNNs by up to 2.76-ns. The power consumption for the proposed interface circuit was measured to be 29.7-uW with a current of 33-uA at a 0.9-V nominal supply voltage.
- KSP Keywords
- 28 nm, Address-Event-Representation, Challenging issues, Inter-chip communication, Interface circuit, Multi-pipeline, Power Consumption, Spike transmission, Supply voltage, asynchronous interface, full-custom