BROWSE
Detail
Conference Paper
Florian: Developing a Low-power RISC-V Multicore Processor with a Shared Lightweight FPU
Cited 4 time in 
Share 
Share
- Authors
- Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
- Issue Date
- 2023-08
- Citation
- International Symposium on Low Power Electronics and Design (ISLPED) 2023, pp.1-6
- Language
- English
- Type
- Conference Paper
- Abstract
- As applications running on lightweight RISC-V processors become increasingly diverse and complex, the need for multicore processors supporting floating-point units (FPUs) is riseing, making processor designs using existing open-source RISC-V cores challenging. With the exception of a very few, most open lightweight RISC-V cores are integer cores without FPUs, which greatly reduces the design exploration space, making it impossible to design a processor optimized for each application. For example, most of these applications mainly perform integer operations, but occasionally perform floating-point operations. For them, a multicore processor with FPU per core is overkill and wastes power, which is a critical problem for processors where low-power design is paramount. To address the problem, we propose an external lightweight FPU that can be attached to any RISC-V integer core and a low-power multicore architecture using the designed FPU. For verification, we designed a RISC-V processor that implements all the proposed technologies, prototyped it on an FPGA device, and finally fabricated it as a System-on-Chip. Through experiments, it was confirmed that the proposed technology can cut energy consumption energy by up to 23%.
- KSP Keywords
- Consumption energy, Design Exploration, FPGA device, Floating-point operations, Low-Power design, Multicore architecture, Open source, RISC-V, System-On-Chip(SoC), energy consumption, multi-core processor