ETRI-Knowledge Sharing Plaform

KOREAN
논문 검색
Type SCI
Year ~ Keyword

Detail

Journal Article Novel approach for implementing ternary value logic devices showing negative differential transconductance characteristics by Fowler–Nordheim tunneling
Cited 1 time in scopus Share share facebook twitter linkedin kakaostory
Authors
Jieun Kim, Jung Wook Lim
Issue Date
2023-09
Citation
Materials Science in Semiconductor Processing, v.164, pp.1-6
ISSN
1369-8001
Publisher
Elsevier Ltd.
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1016/j.mssp.2023.107625
Abstract
Ternary value logic (TVL) devices are gaining attention owing to the limitations of binary devices in handling the increasing amount of information. However, the development of ternary devices has been hindered by the complex structures and use of materials lacking CMOS compatibility. This study presents a novel approach to develop ultra-simple TVL devices using thin-tunnel gate dielectrics of AlOx films and TiO2 channel layer. TVL devices are obtained by employing TiO2-based transistors with AlOx films as an oxide tunneling dielectric layer. The device exhibits typical transistor switching characteristics at low gate voltage (VG) and negative differential transconductance owing to Fowler−Nordheim tunneling current at high VG. The reversible implementation of three states, namely, ON, intermediate (INT), and OFF, with the same probability, is demonstrated with excellent reproducibility even after 200 cycles. A circuit is constructed to demonstrate the three output voltage states with respect to the input voltage by connecting the TVL device to a resistor. Additionally, the value and width of the plateau region of the INT output voltage state can be tuned by adjusting the variable resistance values. These highly simplistic TVL devices have the potential for application in low-power, highly integrated, and ultra-miniature electronic devices, thanks to their high level of CMOS compatibility.
KSP Keywords
CMOS compatibility, Channel layer, Complex structure, Gate voltage, Input voltage, Novel approach, Output Voltage, Plateau region, Tunneling current, Ultra-miniature, Variable resistance