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Design of Parallel Scrambler in High-speed Serial Protocol
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- Authors
- Won Ok Kwon, Seong Woon Kim, Pyung Choi
- Issue Date
- 2010-07
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2010, pp.59-62
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper describes an implementation and analysis of scrambler/descrambler for physical layer of high-speed serial protocols like as PCI Express. On high frequency transmission in serial protocol, electromagnetic interference noise significant effect on signal integrity. The repetitive patterns can be eliminated by scrambling the transmitted data. Linear Feedback Shift Register is used to scramble the data at high-speed serial protocol. This paper proposes the 16-bit parallel scrambler algorithm and design using the precalculation concept. Parallel scrambler/descrambler has precalculators that can get the value to be used as input value of LFSR in next state. We designed scrambling/descrambling architecture to register transfer level and prove the compatibility by function simulation. To verify hardware compatibility, it is implemented on FPGA and tested by protocol analyzer.
- KSP Keywords
- Electromagnetic interference(EMI), Function Simulation, High frequency(HF), High-speed serial, Linear feedback shift registers(LFSR), PCI-Express(PCIe), Physical Layer, Protocol analyzer, Register Transfer Level, Repetitive patterns, Signal Integrity(SI)