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Conference Paper
Laser-Assisted Bonding with Compression (LABC) based Tiling Bonding Technology, Enabling Technology for Chiplet Integration
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- Authors
- Kwang-Seong Choi, Jiho Joo, Gwang-Mun Choi, Chanmi Lee, Ki-Seok Jang, Jin-Hyuk Oh, Jungho Shin, Ho-Gyeong Yun, Seok Hwan Moon, Yoon-Hwan Moon, Yong-Sung Eom
- Issue Date
- 2023-06
- Citation
- Electronic Components and Technology Conference (ECTC) 2023, pp.1385-1389
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Chiplet integration technology is already being used to effectively develop SoCs optimized for custom applications. The method can also practically solve the yield problems of semiconductor advanced nodes, and is considered one of the main technologies that will determine the international competitiveness of system semiconductors. One of the real challenges of chiplet integration is how to effectively integrate small chips with numerous extremely fine-pitch bumps at a wafer-level or a panel-level. Conventionally, there are two known ways to implement chiplet integration: Chip-on-Wafer (CoW) and Wafer-on-Wafer (WoW). From the viewpoint of the bonding process, reflow, thermocompression bonding, and hybrid bonding processes are considered candidate technologies. So far, however, none of these technologies have met the requirements of chiplet integration simultaneously, such as processing many dies from multiple, different wafers, enhanced productivity, known-good-dies (KGDs), yield management, low cost, and so on. To simultaneously solve these problems, we propose a tiling bonding process based on Laser-Assisted Bonding with Compression (LABC) technology, with our proprietary bonding materials for LABC. The approach takes advantage of both the CoW and WoW bonding processes. It can utilize the KGDs from multiple, different wafers, and perform bonding over a relatively larger area than CoW. It can also achieve higher productivity than the CoW bonding process because certain adjacent areas can be repeatedly processed, meaning wafer-level or panel-level processes can be performed in a very short time. Moreover, the cycle time of a single tiling bonding process can be less than 5 seconds, resulting in significantly higher manufacturability than the aforementioned bonding processes. In this paper, we explain the principle of the tiling bonding process, and compare it with other bonding technologies. The properties of the bonding materials, a key enabling technology for the tiling process, will be introduced. Using the tiling process, a prototype of a mini LED display was demonstrated as a test study.
- KSP Keywords
- Bonding process, Bonding technology, Chip-on-Wafer, Enabling technologies, Hybrid bonding, Integration technology, LED display, Laser-Assisted Bonding, Low-cost, Short time, Test study