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Journal Article
A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration
- Authors
- Sunghyun Bae, Sewon Lee, Siheon Seong, Sunwoo Kong, Bonghyuk Park, Minjae Lee
- Issue Date
- 2023-09
- Citation
- IEEE Access, v.11, pp.104323-104332
- ISSN
- 2169-3536
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Language
- English
- Type
- Journal Article
- Abstract
- This paper introduces a completion-aware background sequential capacitor mismatch calibration technique for SAR ADC. The proposed method sequentially corrects capacitor mismatch from the lower to the upper bits in the CDAC. This calibration method can automatically detect when calibration is complete, thereby improving power efficiency by terminating calibration activities. This approach mitigates the trade-off between adaptation speed and calibration code variation, enhancing correction speed. Moreover, the sequential calibration demonstrates stable adaptation in unpredictable input environments. The ADC developed in this study utilizes 55-nm ultra-low power (ULP) CMOS technology, operates at a speed of 1 MS/s, and consumes
$43~\mu W$
- KSP Keywords
- CMOS Technology, Calibration method, Capacitor Mismatch Calibration, Power Efficiency, Trade-off, Ultralow power(ULP), calibration technique, successive approximation analog-to-digital converter(SAR ADC)
This work is distributed under the term of Creative Commons License (CCL)
(CC BY NC ND)
(CC BY NC ND)
