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Conference Paper
Scalable Multi-layered Real-time Holography Processor Architecture with High Bandwidth Memory (HBM)
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- Authors
- Wonok Kwon, Sanghoon Cheon
- Issue Date
- 2024-05
- Citation
- Society for Information Display (SID) International Symposium 2024, pp.1563-1566
- Language
- English
- Type
- Conference Paper
- Abstract
- In this paper, we present a fast and efficiently scalable 3D holographic video processor using a layer-based method using a modified inverse Fresnel transform. In our previous paper, we designed a single-layer holographic core using a fixed-point model and tested its operation on an FPGA. This paper implements an 8-layer, 15FPS real-time hologram processor by receiving RGB and depth input. For fast CGH processing, we utilized HBM memory, which is faster than DDR4, to store FFT results. After applying 2× linear interpolation, the implemented real-time holography processor converts into real-time holograms using a 4K color space light modulator
- KSP Keywords
- Color Space, Fresnel transform, Layer-based, Linear interpolation, Point model, Processor architecture, Real-time holography, Single-layer, fixed point, high bandwidth memory(HBM), light modulator