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An Efficient Ku-Band Two-Way Vertical-like Power-Combining Power Amplifier using Merged Inter-stage Transformers Achieving 23-23.4 dBm Psat and 45.2-46.6% Peak PAE in 65nm CMOS
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- Authors
- Joon-Hyung Kim, Jeong-Taek Lim, Jae-Eun Lee, Jae-Hyeok Song, Jeong-Taek Son, Min-Seok Baek, Eun-Gyu Lee, Sunkyu Choi, Han-Woong Choi, Seong-Mo Moon, Dongpil Chang, Choul-Young Kim
- Issue Date
- 2024-06
- Citation
- Radio Frequency Integrated Circuits (RFIC) Symposium 2024, pp.299-302
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- We propose a novel power combining PA architecture that cleverly utilizes metal stacks to achieve both high output power and efficiency while maintaining a compact chip size in CMOS. Through the adoption of a two-way vertical-like power combining PA architecture featuring the merged inter-stage transformers, a PA with high efficiency and an area reduction of approximately 50% (about the size of a single PA) can be obtained. This architecture was implemented using a 65nm bulk CMOS process, and its feasibility was verified through precise measurements. The proposed PA demonstrates a gain of 26-27.3 dB, a Psat of 23-23.4 dBm, peak PAE of 45.2-46.6%, a P1dB of 22.7-22.9 dBm, and PAE1dB of 44.2-45.5% in the 13-15 GHz range. When tested using a 1-CC 64-QAM OFDM signal (PAPR 11.2 dB), the PA achieves an average output power of 16.9-17.7 dBm and an average PAE of 22-24.1% at 13-15 GHz (at -25 dB EVMrms).
- KSP Keywords
- 15 GHz, 64-QAM, 65nm CMOS, Area Reduction, Bulk CMOS, CMOS Process, GHz range, Inter-stage, Ku-Band, OFDM signals, Output power and efficiency