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Journal Article
10‐GHz band 2 × 2 phased‐array radio frequency receiver with 8‐bit linear phase control and 15‐dB gain control range using 65‐nm complementary metal–oxide–semiconductor technology
- Authors
- Seon-Ho Han, Bon-Tae Koo
- Issue Date
- 2024-08
- Citation
- ETRI Journal, v.46, no.4, pp.708-715
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원
- Language
- English
- Type
- Journal Article
- Abstract
- We propose a 10‐GHz 2 × 2 phased‐array radio frequency (RF) receiver with an 8‐bit linear phase and 15‐dB gain control range using 65‐nm complementary metal–oxide–semiconductor technology. An 8 × 8 phased‐array receiver module is implemented using 16 2 × 2 RF phased‐array integrated circuits. The receiver chip has four single‐to‐differential low‐noise amplifier and gain‐controlled phase‐shifter (GCPS) channels, four channel combiners, and a 50‐Ω driver. Using a novel complementary bias technique in a phase‐shifting core circuit and an equivalent resistance‐controlled resistor–inductor–capacitor load, the GCPS based on vector–sum structure increases the phase resolution with weighting‐factor controllability, enabling the vector–sum phase‐shifting circuit to require a low current and small area due to its small 1.2‐V supply. The 2 × 2 phased‐array RF receiver chip has a power gain of 21 dB per channel and a 5.7‐dB maximum single‐channel noise‐figure gain. The chip shows 8‐bit phase states with a 2.39° root mean‐square (RMS) phase error and a 0.4‐dB RMS gain error with a 15‐dB gain control range for a 2.5° RMS phase error over the 10 to10.5‐GHz band.
- KSP Keywords
- Capacitor load, Control range, Controlled resistor, Core circuit, Equivalent resistance, GHz band, Gain Control, Linear phase, Phase control, Phase resolution, Power gain
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
