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Conference Paper STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs
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Authors
Kyuseung Han, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Hyunseok Kwak, Woojoo Lee
Issue Date
2024-08
Citation
International Symposium on Low Power Electronics and Design (ISLPED) 2024, pp.1-6
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1145/3665314.3670803
Abstract
Developing low-power neuromorphic processors capable of inferring outcomes from SNN Frameworks presents significant challenges, largely due to the gap between frameworks and analog circuit-based SNNs. This paper analyzes the root of this gap as stemming from over/underflow issues and proposes mixed-signal neurons as a solution, further developing a neural core composed of these neurons. In the development of the neural core, we incorporate a design methodology for application-specific neural core optimization. We advance to develop a neural engine as an independent IP, ultimately introducing the snnTorch Architecture (STARC), an integrated mixed-signal neuromorphic processor architecture. The STARC processor, developed as a prototype, demonstrates operational correctness and exceptional low-power performance.
KSP Keywords
Circuit-based, Low-Power, Processor architecture, analog circuits, application specific, design methodology, mixed signal, power performance