상세정보
학술대회
Implementation of an Encoder based on Parallel Structure for LTE Systems
- 발행일
- 201004
- 출처
- Wireless Communications and Networking Conference (WCNC) 2010, pp.1-6
- 협약과제
- 10MI1100, 4세대 이동통신을 위한 적응 무선접속 및 전송 기술개발, 김영진
- 초록
- The operation time of the encoder is one of the important implementation issues to meet the timing requirements of LTE systems since the encoder is based on binary operations. In this paper, we propose the design and implementation of an encoder based on parallel structure for LTE systems. Through 8 bits parallel processing of the CRC attachment, code block segmentation, and parallel processor, we could perform the engines for turbo coding and rate matching of each code block in parallel fashion. Experimental results show that although the FPGA slice register, slice LUT, block ram, and clock period of the proposed scheme are 18, 19, 22, and 6% larger than those of the conventional method based on serial processing respectively, our parallel structure reduces the latency about 19 ~ 70% compared with the serial structure. In particular, our approach is more latency efficient in case the encoder processes numerous code blocks. ©2010 IEEE.
- KSP 제안 키워드
- Block RAM, Clock Period, Code block segmentation, Conventional methods, LTE systems, Parallel Processing, Parallel processor, Parallel structure, Serial processing, Turbo coding, design and implementation