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Implementation of High-speed LDPC decoder using SDFEC for 5G-adv and 6G
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- Authors
- Yong Su Lee, Jun Woo Kim, Young Jin Moon, Seungjae Bahng, Jang-won Moon, Hoon Lee, JungSook Bae
- Issue Date
- 2024-10
- Citation
- International Conference on Information and Communication Technology Convergence (ICTC) 2024, pp.1037-1039
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper discusses the implementation technology aimed at reducing the power consumption and weight of a wireless backhaul system mounted on drones, which is used to temporarily establish high-speed communication networks in preparation for disasters. To implement a drone-mounted modem capable of high-speed wireless data communication at speeds of over 1 Gbps, we utilized the XCZU48DR (Xilinx Zynq UltraScale+ RF -SoC) that includes an LDPC (Low Density Parity Check Code) decoder core. By using the four SDFEC (Soft Decision Forward Error Correction) cores within the XCZU48DR, we performed LDPC (Low Density Parity-check Code) decoding and achieved decoding performance of over 1 Gbps. Therefore, this paper presents the implementation details of a high-speed LDPC decoder using SDFEC with performance exceeding 1 Gbps.
- KSP Keywords
- Forward Error Correction(FEC), High-speed communication networks, LDPC Decoder, Low Density Parity Check(LDPC), Parity check codes, Power Consumption, Soft-decision, Wireless Data Communication, Xilinx ZYNQ, decoding performance, high-speed wireless