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Journal Article
Mixed‐mode SNN crossbar array with embedded dummy switch and mid‐node pre‐charge scheme
- Authors
- Kwang-Il Oh, Hyuk Kim, Taewook Kang, Sung-Eun Kim, Jae-Jin Lee, Byung-Do Yang
- Issue Date
- 2024-10
- Citation
- ETRI Journal, v.46, no.5, pp.865-877
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a membrane computation error-minimized mixed-mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid-node pre-charge scheme to construct a high-precision current-mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28-nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 μW of power consumed. Moreover, the peak-to-peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample-wise random variations.
- KSP Keywords
- 28 nm, CMOS Process, Charge sharing(CS), Current-mode(CM), FDSOI CMOS, Parasitic Capacitance, Pre-charge, crossbar array, high-precision, mixed-mode, neural network(NN)
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
