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Journal Article
Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks
- Authors
- Sung-Eun Kim, Kwang-Il Oh, Taewook Kang, Sukho Lee, Hyuk Kim, Mi-Jeong Park, Jae-Jin Lee
- Issue Date
- 2024-10
- Citation
- ETRI Journal, v.46, no.5, pp.878-889
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원
- Language
- English
- Type
- Journal Article
- Abstract
- To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal–oxide–semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.
- KSP Keywords
- 28 nm, Fully Depleted(FD), Fully depleted silicon on insulator(FD SOI), Global clock, Human brain, Interface circuit, Silicon On Insulator(SOI), asynchronous interface, full-custom, neural network(NN), spiking neural networks
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
