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Conference Paper
A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, Area Efficient Techniques for Chiplet-Based AI processors in 12-nm CMOS
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- Authors
- Jaewoong Choi, Yi-Gyeong Kim, Juyeob Kim, Jaehoon Chung, Young-Deuk Jeon, Min-Hyung Cho, Sujin Park, Jinho Han
- Issue Date
- 2024-11
- Citation
- Asian Solid-State Circuits Conference (A-SSCC) 2024, pp.1-3
- Language
- English
- Type
- Conference Paper
- KSP Keywords
- Area-Efficient, low power