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Journal Article
Low-Complexity Architecture for High-Speed 50G-PON LDPC Decoder
- Authors
- Kon-Woo Kwon, Kwangok Kim, Kyeonghwan Doo, Hwanseok Chung, Jeong Woo Lee
- Issue Date
- 2025-02
- Citation
- IEEE Access, v.13, pp.28751-28765
- ISSN
- 2169-3536
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Language
- English
- Type
- Journal Article
- Abstract
- We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.
- KSP Keywords
- Cyclic property, Cyclic shift, FPGA board, High Speed, High throughput, Implementation complexity, LDPC Decoder, Low complexity, Low level, Quasi-Cyclic, Resource utilization
This work is distributed under the term of Creative Commons License (CCL)
(CC BY NC ND)
(CC BY NC ND)
