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Investigation of Chlorine-Induced Damage in Oxide Semiconductor Transistors
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- Authors
- Jae Won Na, Seungbin Lee, Hyeonhong Min, Gwanghyeon Jang, Minseop Song, I. Sak Lee, Jong-Heon Yang, Min Jung Kim, Kwun-Bum Chung, Si Joon Kim
- Issue Date
- 2025-07
- Citation
- ACS Applied Electronic Materials, v.7, no.13, pp.6128-6136
- ISSN
- 2637-6113
- Publisher
- American Chemical Society
- Language
- English
- Type
- Journal Article
- Abstract
- As interest in using indium-gallium-zinc oxide (IGZO) for next-generation memory applications grows, understanding its reliability under fabrication-relevant conditions has become essential. In dynamic random-access memory (DRAM), chlorine (Cl) contamination─typically introduced during TiCl
4 -based titanium nitride (TiN) electrode deposition─is a known source of reliability degradation. To enable its reliable application in advanced DRAM and ferroelectric field-effect transistor (FeFET)-based memory technologies, foundational investigations into potential failure mechanisms such as chlorine-induced damage (CID) are critically needed. In this work, CID at the IGZO/SiO2 interface was evaluated by applying Cl plasma treatment for 0 to 8 min prior to IGZO deposition. This enabled selective Cl incorporation at the dielectric surface without causing physical or chemical damage, as confirmed by surface analysis indicating physisorption without morphological degradation. However, electrical performance worsened with Cl exposure: mobility decreased from 11.97 to 8.78 cm2/V·s, threshold voltage (Vth ) increased from 0.95 to 2.27 V, and subthreshold swing increased from 0.30 to 0.48 V/dec. After 10,000 s of positive bias stress (PBS) and negative bias temperature stress (NBTS), Vth increased from 4.88 to 6.83 V (PBS) and decreased from −1.12 to −3.86 V (NBTS), respectively. AC transconductance analysis revealed a significant increase in deep-level trap states, consistent with XPS depth profiling results showing the formation of In-Cl bonding and a rise in nonlattice oxygen (Vo )-related O 1s components near the IGZO/SiO2 interface. These results show that even minor Cl incorporation at the interface alters defect states in IGZO, leading to trap formation. This highlights the need for Cl-mitigation to ensure reliable IGZO integration in future memory devices.
- KSP Keywords
- 3 V, 48 V, Bias Stress, Bias temperature stress, Chemical damage, Cl incorporation, Deep level, Depth profiling(DP), Dynamic random-access memory(DRAM), Electrical performance, Failure mechanisms