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Conference Paper
Oxide TFT Integration for DRAM Cell Transistor Applications
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- Authors
- Jae Won Na
- Issue Date
- 2025-07
- Citation
- International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD) 2025, pp.75-77
- Language
- English
- Type
- Conference Paper
- Abstract
- As DRAM scales beyond the 10 nm node, conventional silicon-based cell transistors face growing limitations in leakage, cell area, and integration complexity. Oxide thin-film transistors (TFTs), known for their ultralow off-state current and compatibility with back-end-of-line (BEOL) processes, have emerged as promising alternatives. This work examines two oxide TFT-based DRAM paths: capacitorless 2T-0C architectures utilizing floating-node charge storage, and 1T-1C structures based on vertical oxide channel transistors with stacked capacitors. Recent academic and industrial efforts have demonstrated these approaches across planar and vertical configurations, achieving long retention, 4F2 scaling, and monolithic 3D stackability. The comparative analysis presented here highlights the potential of oxide TFTs to extend DRAM scaling and integration beyond conventional design boundaries.
- KSP Keywords
- Cell area, Charge storage, Comparative analysis, DRAM Cell transistor, Oxide TFTs, Oxide channel, Sampling Time(Ts), Silicon-based, Thin-Film Transistor(TFT), back-end-of-line, conventional design