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Journal Article Operation-level scheduling framework for efficient deep learning inference on embedded systems using directed acyclic graphs
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Authors
Mooseop Kim, SuGil Choi, Sungjun Wang, Chi Yoon Jeong
Issue Date
2026-01
Citation
ETRI Journal, v.권호미정, pp.1-15
ISSN
1225-6463
Publisher
John Wiley & Sons
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.4218/etrij.2025-0201
Abstract
This study presents an operation-level scheduling framework for efficient deep learning inference on heterogeneous embedded systems. Motivated by the observation that deep neural networks comprise diverse operations in which the execution latency is highly dependent on the target hardware and input dimensions. The framework hypothesizes that accurate latency prediction and fine-grained scheduling of individual operations reduce end-to-end inference time. It follows a three-stage approach: (i) offline profiling of operation latencies across varying input sizes and devices; (ii) training latency prediction models using input-aware features; and (iii) directed acyclic graph-based runtime scheduling to assign each operation to a central processing unit, graphics processing unit, or both. The framework is evaluated on two embedded platforms (Jetson Nano and ODROID-XU4) and demonstrates an inference latency reduction of up to 74% across multiple deep learning models. These results indicate that the framework is adaptable, lightweight, and effective for resource-constrained artificial intelligence deployments.
Keyword
central processing unit-graphics processing unit co-execution, deep learning inference, embedded system, heterogeneous computing
KSP Keywords
Co-execution, Deep neural network(DNN), Directed acyclic graphs, Embedded Platforms, End to End(E2E), Fine grained(FG), Fine-grained scheduling, Graph-based, Latency prediction, Latency reduction, Level scheduling
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
Type 4: