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Conference Paper
FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI
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- Authors
- Eun-Su Cho, Jongin Choi, Jeongmin Jin, Jae-Jin Lee, Woojoo Lee
- Issue Date
- 2026-04
- Citation
- Design, Automation & Test in Europe Conference (DATE) 2026, pp.1-7
- Publisher
- European Design and Automation Association
- Language
- English
- Type
- Conference Paper
- Abstract
- Machine unlearning, driven by privacy regulations and the "right to be forgotten," is increasingly needed at the edge, yet server-centric or retraining-heavy methods are impractical under tight computation and energy budgets. We present FiCABU (Fisher-based Context-Adaptive Balanced Unlearning), a SW–HW co-design that brings unlearning to edge AI processors. FiCABU combines (i) Context-Adaptive Unlearning, which begins edits from back-end layers and halts once the target forgetting is reached, with (ii) Balanced Dampening, which scales dampening strength by depth to preserve retain accuracy. These methods are realized in a full RTL design of a RISC-V edge AI processor that integrates two lightweight IPs for Fisher estimation and dampening into a GEMM-centric streaming pipeline, validated on an FPGA prototype and synthesized in 45 nm for power analysis. Across CIFAR-20 and PinsFaceRecognition with ResNet-18 and ViT, FiCABU achieves random-guess forget accuracy while matching the retraining-free Selective Synaptic Dampening (SSD) baseline on retain accuracy, reducing computation by up to 87.52% (ResNet-18) and 71.03% (ViT). On the INT8 hardware prototype, FiCABU further improves retain preservation and reduces energy to 6.48% (CIFAR-20) and 0.13% (PinsFaceRecognition) of the SSD baseline. In sum, FiCABU demonstrates that back-end–first, depth-aware unlearning can be made both practical and efficient for resource-constrained edge AI devices.
- KSP Keywords
- 5 nm, Co-design, FPGA prototype, Machine Unlearning, Power Analysis, Privacy regulations, RISC-V, RTL Design, Resource-constrained, Right to be forgotten, Server-centric