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7 GHz 비대칭 3-Stack 구조의 CMOS SPDT 스위치 설계
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- Issue Date
- 2026-06
- Citation
- 대한전자공학회 학술 대회 (하계) 2026, pp.1-3
- Publisher
- 대한전자공학회
- Language
- Korean
- Type
- Conference Paper
- Abstract
- This paper presents a 7 GHz SPDT switch using an asymmetric 3-stack transistor structure to improve insertion loss and isolation. Unlike conventional symmetric structures, the proposed design optimizes device stacking and sizing for performance enhancement. Simulation results show low insertion loss of 1.03 dB in transmit mode and 1.09 dB in receive mode, along with improved isolation and impedance matching. Power simulations confirm high linearity, with minimal gain compression up to 28.8 dBm and stable operation from 6.4 GHz to 7.6 GHz. These results demonstrate that the proposed technique is effective for enhancing RF switch performance in high-frequency applications.
- KSP Keywords
- 6 GHz, Gain compression, High frequency(HF), High-frequency applications, Impedance matching, Low insertion loss, RF switch, SPDT Switch, Stable operation, high linearity, performance enhancement