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저전력 저면적 LPDDR6 메모리 인터페이스 수신부 설계
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- Issue Date
- 2026-06
- Citation
- 대한전자공학회 학술 대회 (하계) 2026, pp.1-2
- Publisher
- 대한전자공학회
- Language
- Korean
- Type
- Conference Paper
- Abstract
- This paper presents a LPDDR6 memory interface receiver (RX) for low-power and low-area. The proposed receiver consists of an input multiplexer (MUX), an input buffer, an receiver circuit based on inverter logics, and a digitally controlled delay line. The receiver circuit using the inverters provides the high speed operation of data recovery without complicate analog amplifiers and comparators. The proposed receiver is implemented and simulated a 12nm CMOS technology. The power consumption and efficiency of the proposed receiver is a 2.136mW and a 0.107pJ/bit.
- KSP Keywords
- CMOS Technology, Data recovery, Digitally controlled, Input Buffer, Low Power, Memory interface, high-speed operation, low-area, receiver circuit