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Dual Damascene 배선공정 실리콘 인터포저의 칩렛 인터커넥트 설계
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- Issue Date
- 2026-06
- Citation
- 대한전자공학회 학술 대회 (하계) 2026, pp.1-2
- Publisher
- 대한전자공학회
- Language
- Korean
- Type
- Conference Paper
- Abstract
- This paper presents the design of UCIe-based chiplet interconnects for silicon interposers using a dual damascene metallization process. Due to process limitations such as 1 μm metal thickness, signal integrity is degraded. To address this, three interconnect structures were designed and evaluated through EM and SI simulations at 32 GT/s. The results show that the proposed structures maintain acceptable eye-diagram performance despite limited interconnect thickness.
- KSP Keywords
- Dual damascene, Eye Diagram, Interconnect structures, Metallization process, Signal Integrity(SI), silicon interposer