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A D-band CMOS Beamforming Receiver Module with Linearly Arranged Antenna
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- Authors
- Sunwoo Kong, Seunghun Wang, Hui-Dong Lee, Seunghyun Jang, Bonghyuk Park, Dongphil Jang
- Issue Date
- 2026-06
- Citation
- Vehicular Technology Conference (VTC) 2026 (Spring), pp.1-5
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper proposes a complementary metal-oxide semiconductor (CMOS) beamforming receiver chip architecture operating in the D-band and experimentally verifies the feasibility of low-cost sub-THz operation. An alternating connection scheme for adjacent antennas is presented for a scalable beamforming architecture utilizing a linearly arranged four-channel chip. The D-band CMOS receiver chip comprises low-noise amplifiers (LNAs), active phase shifters, a 4-to-1 power combiner, and a frequency down-converter with a local oscillator (LO). The 9-bit active phase shifter achieves high spatial resolution suitable for D-band applications. The measured gain of the chip demonstrates a peak of approximately 15 dB, with a 3-dB bandwidth ranging from 142 GHz to 155 GHz. Measured over-the-air (OTA) results demonstrate high-resolution beamforming capability with a consistent 13-degree 3-dB beamwidth across steering angles of -30, -15, and 0 degrees.
- Keyword
- Beamforming, CMOS, D-Band, Receiver
- KSP Keywords
- 3-dB bandwidth, 55 GHz, CMOS Receiver, Complementary metal-oxide-semiconductor(CMOS), Connection Scheme, D-band, Four-Channel, High spatial resolution, Local Oscillator, Low-noise amplifier(LNA), Metal-oxide(MOX)