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Conference Paper
Impact of Gate Architecture on Device Performance in Scaled GaN HEMTs
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- Authors
- Hyun-Wook Jung, Sung-Jae Chang, Ho-Kyun Ahn, Dong-Min Kang
- Issue Date
- 2026-07
- Citation
- International Symposium on the Physics of Semiconductors and Applications (ISPSA) 2026, pp.1-1
- Publisher
- 대한물리학회
- Language
- English
- Type
- Conference Paper
- Abstract
- This study presents a comparative study of planar-gate and T-gate GaN HEMTs with gate lengths scaled from 450 to 60 nm. The impacts of LG scaling and gate architecture on DC and RF performance are systematically examined. As LG decreases, both devices show increased ID and gm, while strong short-channel effects emerge at LG = 100 nm, causing pronounced DIBL and VTH roll-off. The T-gate exhibits superior high-frequency performance, achieving fT/fmax of 83/127 GHz at LG = 60 nm, compared with 47/79 GHz for the planar-gate. Parasitic analysis reveals that the T-gate provides lower extrinsic capacitance (0.48 pF/mm), enabling higher speed and reduced parasitic delay. Overall, the results confirm that the T-gate offers stronger immunity to short-channel effects than the planar-gate structure, maintaining excellent RF performance even under aggressive LG scaling.
- KSP Keywords
- 79 GHz, AND gate, DC and RF performance, GaN HEMT, High frequency(HF), High-frequency performance, Planar-gate, T-Gate, comparative study, device performance, extrinsic capacitance