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Three Stacked Ka-Band Bulk CMOS High Output Power Amplifier for Satellite Terminal
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- Authors
- Bonghyuk Park, Hui-Dong Lee, Sunwoo Kong, Dong-Pil Chang
- Issue Date
- 2026-07
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2026, pp.1-4
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents the design and experimental validation of a Ka-band power amplifier (PA) implemented in a 65-nm bulk CMOS technology for low-earth-orbit (LEO) satellite terminal applications. The proposed amplifier adopts a two-stage topology in which the output stage employs a vertically stacked three-transistor structure to enhance voltage handling and output power capability. Measurement results show that the amplifier achieves a small-signal gain of 17.7 dB and an output 1-dB compression point (OP1dB) of 13.46 dBm at 27 GHz with a 3-V supply voltage. At 31 GHz, the measured gain is 14.46 dB with an OP1dB of 13.55 dBm under the same supply condition. The measured results demonstrate the feasibility of the proposed CMOS PA architecture for Ka-band LEO satellite communication terminals.
- Keyword
- LEO satellite terminal, power amplifier, CMOS 65nm, beam-former
- KSP Keywords
- 1-dB compression point, Bulk CMOS, CMOS PA, CMOS Technology, Experimental validation, LEO Satellite, Low Earth Orbit(LEO), Output Stage, Small signal gain, Supply voltage, Two-Stage