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Conference Paper
A 20-dBm Two-Stage CMOS Power Amplifier for 6G Upper-Mid Band Transmit Beamformer ICs
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- Authors
- Hui Dong Lee, Seunghun Wang, Bonghyuk Park, Sunwoo Kong, Dong-Pil Chang
- Issue Date
- 2026-07
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2026, pp.1-3
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- The proposed PA is implemented in a TSMC 65- nm bulk CMOS process and adopts a two-stage gain architecture to achieve an overall gain exceeding 20 dB. To achieve high output power under CMOS breakdown limitations, the output stage employs a three-stacked PA cell, while a neutralization capacitor is utilized to improve stability against parasitic feedback. The fabricated PA achieves a measured gain of 21.5 dB at 8 GHz with a 2-dB bandwidth from 7.5 to 8.7 GHz. The measured saturated output power and output P1dB are 22.1 dBm and 18.2 dBm, respectively, demonstrating suitability for upper-mid band beamformer transmit front-ends.
- Keyword
- 6G, upper-mid band, CMOS power amplifier, beamformer IC, stacked PA, neutralization, TSMC 65 nm
- KSP Keywords
- 65 nm, Bulk CMOS, CMOS Process, CMOS power amplifier, Output Stage, Saturated output power, Transmit beamformer, Two-Stage, high output power, power amplifiers(PAs)