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A Compact Dual-Mode SAR ADC With Mismatch Error Shaping Using Prediction-Error-Free 3-Level Analog Prediction and 1-bit Barrel-Shift Dithering
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- Authors
- Kiho Seong, Jeetaeck Seo, Jeonghun Lee, Sukho Lee, Tony Tae-Hyoung Kim, Kwang-Hyun Baek
- Citation
- IEEE Transactions on Circuits and Systems, Early Access
- ISSN
- 1549-8328
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a compact dual-mode successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring mismatch error shaping (MES). To resolve the input dynamic range loss of conventional MES, a prediction-error-free 3-level analog prediction scheme is proposed. By adaptively bypassing predictions via comparator offsets, this scheme eliminates prediction errors and overcomes the input frequency limitations of conventional prediction methods. Furthermore, to extend the applicability of MES to Nyquist ADCs, a low-overhead 1-bit barrel-shift dithering technique is introduced to randomize capacitive digital-to-analog converter (CDAC) mismatches. Fabricated in a 65nm CMOS process, the prototype occupies a core area of 0.01mm2. In the noise-shaping (NS) mode, the ADC achieves a 78.5dB signal-to-noise-and-distortion ratio (SNDR) and a 91.5dB spurious-free dynamic range (SFDR) over a 31.25kHz bandwidth, yielding a Schreier figure-of-merit ( FoMS ) of 175.8dB. In the Nyquist mode, the 1-bit barrel-shift dithering-based MES improves the SFDR from 69.7dB to 83.7dB at the Nyquist input frequency.
- Keyword
- Analog-to-digital converter (ADC), mismatch error shaping (MES), dual-mode, successive-approximationregister (SAR), noise shaping (NS)
- KSP Keywords
- 3-Level, 65nm CMOS, Analog-to-digital converters(ADCs), CMOS Process, Core area, Distortion ratio, Dithering technique, Dual-Mode, Low overhead, Mismatch error, Prediction error