Quantum computing (QC) emulation is critical for exploring and advancing near-term quantum algorithms, given the ongoing scalability and reliability challenges of quantum hardware. While FPGA-based QC emulators have emerged as efficient alternatives to bridge the gap toward practical quantum computers, most existing solutions depend on high-performance systems, limiting their applicability in embedded and edge environments. In this work, we present a scalable, standalone FPGA-based emulator specialized for resource-constrained systems. Our design targets the Quantum Approximate Optimization Algorithm (QAOA), particularly for the Weighted-MaxCut problem. By leveraging diagonal decomposition and a pipeline-centric hardware architecture, we reduce the computational complexity of QAOA from O(N2) to O(N), where N=2n is the state dimension for n qubits. This reformulation and its architectural codesign significantly reduces hardware overhead, enabling larger qubit configurations on edge-level FPGAs. We encapsulate these optimizations into a hardware accelerator called the Quantum MaxCut Accelerator (QMA), which integrates seamlessly into a RISC-V platform, forming a self-contained emulator. Additionally, we introduce QC Emulator eXpress (QEX), a full-stack automation framework that streamlines QMA integration into configurable RISC-V platforms, significantly facilitating rapid and scalable emulator development and deployment. Through extensive prototyping of various QAOA emulators, our experiments confirm that the proposed QMA achieves energy reductions of up to 907× compared to the CPU-only software baseline under the same standalone FPGA/RISC-V setting and reliably supports up to 9 qubits on a mid-tier FPGA. These results demonstrate the energy efficiency and scalability of the proposed system as a self-contained FPGA/RISC-V platform for edge-local QAOA emulation, prototyping, and HW/SW co-design exploration under resource-constrained conditions.
Approximate optimization, Computational complexity, Design Exploration, Development and deployment, Energy Efficiency(EE), FPGA accelerator, FPGA emulator, HW/SW Co-design, Hardware Architecture, Hardware accelerator, Hardware overhead
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