In 5G New Radio (NR) systems, Quadrature Amplitude Modulation (QAM) is a pivotal process for high-speed data transmission. Conventional hardware implementations face challenges due to the early application of irrational normalization gains, leading to bit-width expansion and increased resource consumption in subsequent blocks like layer mappers and resource mappers. This paper proposes a hardware-friendly QAM modulator architecture that decouples gain multiplication from constellation mapping. By utilizing a unified 64QAM-based core and bit-level operations, the design maintains a 4-bit integer output, reducing subsequent resource consumption by up to 75%. Furthermore, this decoupled structure allows the normalization gain to be integrated and processed simultaneously with finalstage MIMO precoders, optimizing the overall computational efficiency of the transmitter. We provide a detailed description of the architecture through its functional blocks and bit-stream processing methods.
KSP Keywords
Bit stream, Computational Efficiency, Gain scaling, Hardware implementation, Hardware-friendly, High-speed data transmission, Processing Method, QAM modulator, Quadrature Amplitude Modulation(QAM), Resource consumption, Resource-efficient
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