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Conference Paper
Transfer-Aware Kernel Placement on Modern Ryzen APUs
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- Authors
- Yongseung Yu, Yoojin Lim, Choonghan Lee, Jinse Kwon
- Issue Date
- 2026-10
- Citation
- International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 2026, pp.369-372
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Modern Ryzen accelerated processing units (APUs) expose multiple on-die accelerators, such as GPUs and NPUs, whose full utilization requires placement decisions that account for both compute capability and shared-DRAM behavior. In unified-DRAM APUs, the CPU, GPU, and NPU share system DRAM, while each accelerator incurs a different cost to make operands and results visible through the memory system. This letter presents a transfer-aware kernel-placement framework that measures per-accelerator compute and transfer costs and applies a residency-depth cost model to decide placements at compile time for concurrent heterogeneous execution. Evaluation on two Ryzen AI APUs and large language model (LLM)-derived GEMM/GEMV workloads shows that the best placement target changes with transfer-cost amortization and differs across devices and APUs. Compared with a greedy policy that assigns each operation class as a whole to its lowest-cost device, the proposed placement reduces execution time by 18.69% on average on the AI350% and 17.95% on average on the AI365, reaching up to an additional 1.65× speedup in GEMM-dominant scenarios.
- Keyword
- GPU, heterogeneous system, kernel placement, NPU, Ryzen accelerated processing unit (APU).
- KSP Keywords
- Accelerated Processing Unit, Compile time, Execution Time, Heterogeneous systems, Language Models, Memory System, cost model