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Conference Paper 비동기 HDL을 이용한 Clockless 32비트 프로세서 구조 설계
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Authors
김영우, 오명훈, 신치훈, 김성남, 김성운
Issue Date
2011-06
Citation
대한전자공학회 종합 학술 대회 (하계) 2011, pp.1638-1641
Publisher
대한전자공학회
Language
Korean
Type
Conference Paper
Abstract
An asynchronous circuit design methodology is one of the strong candidates to solve problems like timing closure and power consumption in synchronous circuit designs based on a single global clock. To verify the feasibility and efficiency of a large-scaled asynchronous circuit, we designed a clockless 32-bit processor. We designed the processor using an asynchronous HDL and synthesized it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13 um CMOS technology show that the performance and power consumption of the enhanced microarchitecture are improved by 109% and 30% with respect to the basic one. Furthermore, the measured power efficiency is about 163 uW/MHz and is competitive with that of a synchronous counterpart.
KSP Keywords
Asynchronous circuits, CMOS Technology, Global clock, Layout simulation, Power Consumption, Power Efficiency, Timing closure, Top-down design, circuit design, design approach, design methodology