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A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS
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- Authors
- Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon
- Issue Date
- 2011-11
- Citation
- International SoC Design Conference (ISOCC) 2011, pp.405-407
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful layout are adopted to obtain high-resolution in a low-supply. The ADC features 12-bit resolution, 100-MS/s sampling rate, differential nonlinearity (DNL) of 짹0.58 LSB, integral nonlinearity (INL) of 짹2.79 LSB, and power consumption of 30.4 mW. With a sampling frequency of a 100-MS/s and an input of a 2.4 MHz, the ADC achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 59.02 dB and 63.22 dB, at a supply voltage of 1.1 V, respectively. ©2011 IEEE.
- KSP Keywords
- Analog to digital converter(ADC), CMOS Technology, Distortion ratio, High-resolution, Low-voltage circuit, Pipelined ADC, Power Consumption, Sampling frequency, Sampling rate, Signal-to-Noise, Supply voltage