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A 166.7 Mhz 1920×1080 60fps H.264/SVC Video Decoder
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- Authors
- Seung Hyun Cho, Seong Mo Park, Nak-Woong Eum
- Issue Date
- 2011-11
- Citation
- International SoC Design Conference (ISOCC) 2011, pp.278-281
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- In this paper, a hardware design of an H.264/SVC video decoder is presented. Large size inter-coded pictures in a high frame rate require a high external memory bandwidth in decoding process. Inter-layer predictions of SVC further increase data transfer from or to an external memory. A cache-based motion compensation to sufficiently reduce overhead cycles for external SDRAM access and the bandwidth requirement is proposed. Much variation of macroblock processing cycles for CABAC decoding is another obstacle to design a SVC video decoder with macroblock based pipelining scheme. A frame level delaying method is proposed to remove the cycle variations, so that the decoder works with a steady throughput. The proposed SVC decoder shows HD1080p 60fps of decoding capability operating at 166.7MHz. ©2011 IEEE.
- KSP Keywords
- Data transfer, High frame rate(HFR), Inter-layer, Memory bandwidth, Motion Compensation(MoCo), Video decoder, bandwidth requirements, external memory, frame rate(FR), hardware design, large size