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학술대회
A 166.7 Mhz 1920×1080 60fps H.264/SVC Video Decoder
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- 발행일
- 201111
- 출처
- International SoC Design Conference (ISOCC) 2011, pp.278-281
- 협약과제
- 11PR2100, IPTV 융합 단말 고도화 지원 기술 개발, 김영일
- 초록
- In this paper, a hardware design of an H.264/SVC video decoder is presented. Large size inter-coded pictures in a high frame rate require a high external memory bandwidth in decoding process. Inter-layer predictions of SVC further increase data transfer from or to an external memory. A cache-based motion compensation to sufficiently reduce overhead cycles for external SDRAM access and the bandwidth requirement is proposed. Much variation of macroblock processing cycles for CABAC decoding is another obstacle to design a SVC video decoder with macroblock based pipelining scheme. A frame level delaying method is proposed to remove the cycle variations, so that the decoder works with a steady throughput. The proposed SVC decoder shows HD1080p 60fps of decoding capability operating at 166.7MHz. ©2011 IEEE.
- KSP 제안 키워드
- Data transfer, Hardware Design, High frame rate, Inter-layer, Memory bandwidth, Motion Compensation(MoCo), bandwidth requirements, external memory, large size, video decoder