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학술대회 A 4-GHz All Digital Fractional-N PLL with LowPower TDC and Big Phase-Error Compensation
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저자
이자열, 박미정, 민병훈, 김성도, 박문양, 유현규
발행일
201109
출처
Custom Integrated Circuits Conference (CICC) 2011, pp.1-4
DOI
https://dx.doi.org/10.1109/CICC.2011.6055303
협약과제
11MB1500, 차세대 무선 융합 단말용 Advanced Digital RF 기술 개발, 유현규
초록
This paper presents an all-digital fractional-N PLL with a low-power TDC operating at the retimed reference clock. Two retimed reference clocks are employed to implement the proposed TDC estimating the fractional phase error between the reference clock and CKV clock. The application of the retimed reference clocks to TDC does not only reduce dynamic power in TDC delay inverter chain, but also simplify 琯r estimation including a new T v calculation algorithm. Also, phase-error compensation block is presented to compensate for the big phase-error change due to timing skew in the output bits produced from variable-phase counter. And loop settling scanning block is invented to shift DCO operation mode and additionally decrease PLL channel switching time for frequency hopping applications. The proposed all-digital PLL represents - 36dBc integrated phase noise (1kHz - 20MHz), 778fs rms jitter, 9.6mW power consumption. The channel switching time of the ADPLL is measured as 630nsec. © 2011 IEEE.
KSP 제안 키워드
All-digital PLL, Calculation algorithm, Channel Switching, Compensation block, Dynamic power, Fractional-N PLL, Low-Power, Operation modes, Phase error compensation, Power Consumption, Reference clock