상세정보
학술대회
A Low Power Discrete-Time Receiver for Triple-Band FM/T-DMB/DAB System-on-Chip
- 발행일
- 201109
- 출처
- European Solid-State Circuits Conference (ESSCIRC) 2011, pp.311-314
- 협약과제
- 10MB2800, 차세대 무선 융합 단말용 Advanced Digital RF 기술 개발, 유현규
- 초록
- This paper presents a low power discrete-time receiver supporting three broadcast services FM, T-DMB and DAB. To meet the requirement of sensitivity, three LNAs are implemented to cover each band. The proposed mixer core is terminated by a common-gate current buffer to improve linearity and merged with a switched-capacitor sampled filter in current mode for low power and low complexity. The filter performs the second-order low-pass filtering with anti-aliasing ratio up to 70 dB at 1.6 MHz bandwidth. The chip is fabricated in a 90 nm CMOS technology and dissipates 11 mA current from 1.2 V supply. The receiver shows 48 dB maximum gain, 60 dB gain control range, 2.7 dB noise figure, and -22/0 dBm IIP3 in LNA high/low gain mode. © 2011 IEEE.
- KSP 제안 키워드
- 6 MHz, 90 nm CMOS technology, Anti-aliasing, Control range, Current-mode(CM), Gain Control, Low-Power, MHz bandwidth, Noise Figure(NF), Switched Capacitor(SC), System-On-Chip(SoC)