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Conference Paper
An LDPC decoder architecture for multi-rate QC-LDPC codes
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- Authors
- Sung-Woo Choi, Gyung-Pyo Kim, Jin-Kyeong Kim
- Issue Date
- 2011-08
- Citation
- International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents a partially parallel LDPC decoder architecture for QC-LDPC codes. In particular, we introduce a check node processing element which is 3-parallel, adjustable to irregular inputs and easily expandable. Furthermore, our decoder is applicable to multi-rate system by simply writing additional data to internal RAM. In another aspect of our work, we can reduce the check-bit message memory significantly by efficient method. Implementation results show that the proposed architecture can support the data rate of 360Mbps in FPGA. © 2011 IEEE.
- KSP Keywords
- Check Node, LDPC Decoder, Multi-rate system, Processing Element, QC-LDPC codes, Quasi-cyclic low-density parity-check(QC-LDPC), data rate, decoder architecture