상세정보
학술대회
An LDPC Decoder Architecture for Multi-Rate QCLDPC Codes
- 발행일
- 201108
- 출처
- International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4
- 협약과제
- 11PI1800, 개방형 mmWave 무선 인터페이스 플랫폼 기술개발, 정현규
- 초록
- This paper presents a partially parallel LDPC decoder architecture for QC-LDPC codes. In particular, we introduce a check node processing element which is 3-parallel, adjustable to irregular inputs and easily expandable. Furthermore, our decoder is applicable to multi-rate system by simply writing additional data to internal RAM. In another aspect of our work, we can reduce the check-bit message memory significantly by efficient method. Implementation results show that the proposed architecture can support the data rate of 360Mbps in FPGA. © 2011 IEEE.
- KSP 제안 키워드
- Check Node, LDPC decoder, Multi-rate system, Processing Element, QC-LDPC codes, Quasi-cyclic low-density parity-check(QC-LDPC), data rate, decoder architecture