상세정보
학술대회
Application Specific Processor for Multi-standard Video Decoding
- 발행일
- 201111
- 출처
- International SoC Design Conference (ISOCC) 2011, pp.436-439
- 협약과제
- 11MB1700, 에너지 스케일러블 벡터 프로세서 선행기술, 엄낙웅
- 초록
- Application-specific instruction processor is a new design methodology to develop optimized processors for specific applications. This paper proposes a new application-specific instruction processor and compiler for multi-standard video decoding. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for multi-standard video decoding, and compiler mapping techniques such as CKF(compiler known function) and inline assembly. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. Compared to the existing ARM processor, the proposed architecture and compiler result in about 20% improvement in video decoding in terms of total cycles as well as smaller hardware complexity. ©2011 IEEE.
- KSP 제안 키워드
- ARM Processor, Application Specific Processor, Hardware complexity, Inline assembly, Multi-Standard, SIMD architecture, Specific applications, design methodology, video decoding