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Conference Paper
Design of Asynchronous 2-Phase Ternary Encoding Protocol Using Multiple-Valued Logic
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- Authors
- Myeong-Hoon Oh, Sung-Nam Kim, Sung Woon Kim
- Issue Date
- 2011-11
- Citation
- International SoC Design Conference (ISOCC) 2011, pp.416-419
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Due to a half transitions for data transfers comparing with conventional 4-phase signalings, level-encoded dual-rail (LEDR) has been widely used in on-chip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers to maintain delay-insensitive encoding. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme, and the circuits are implemented using current-mode multiple-valued logics. In the simulation with 0.25 um CMOS technology, the suggested circuits saves both latency and energy consumption over the wire length of 3 mm. ©2011 IEEE.
- KSP Keywords
- CMOS Technology, Current-mode(CM), Data transfer, Delay-insensitive, Dual-rail, Encoder and Decoder, Global interconnects, Handshake Protocol, Multiple-Valued Logic(MVL), Wire length, encoding scheme