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Design Time Stamp Hardware Unit Supporting IEEE 1588 Standard
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- Authors
- Jae Won Park, Jin Ha Hwang, Won Young Chung, Seung Woo Lee, Yong Surk Lee
- Issue Date
- 2011-11
- Citation
- International SoC Design Conference (ISOCC) 2011, pp.345-348
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Time synchronization is currently becoming more and more important in a range of fields, including location-based services, military services that use satellites, mess production using robots, as well as in measurement and testing. There are two methods of time precision: location-based synchronization and frequency synchronization. IEEE 1588 is one frequency synchronization standard and can be implemented by software time stamping. However, software implementation results in delay and jitter at the application level when packets are delivered, and this can cause problems. The best way to reduce these problems is through hardware implemented time stamping. In addition, hardware resource reuse is better than calculating Delay and Offset in hardware, because calculating is not critical path in IEEE 1588. In this paper, we implement a hardware unit that is compliant with the IEEE 1588 Version 2 standard and provides sub-microsecond accuracy for high-speed networks. The unit reuses hardware resources in the host processor to calculate Delay and Offset. Hardware unit is synthesized with TSMC 65nm technology. It operates at 550MHz clock speed. It is aimed at high performance network processors or Network on a Chip. ©2011 IEEE.
- KSP Keywords
- 5nm technology, Clock speed, Critical path, Design time, Frequency synchronization, Hardware Resources, High performance network, High-speed networks, IEEE 1588, Location-Based Services, Network processor