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Memory Efficient Hardware Design for a 3-Spatial Layer SVC Encoder
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- Authors
- Kyujoong Lee, Chae-Eun Rhee, Hyuk-Jae Lee, Jungwon Kang
- Issue Date
- 2011-08
- Citation
- International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4
- Language
- English
- Type
- Conference Paper
- Abstract
- Spatial scalability in Scalable Video Coding (SVC) enables a video encoder to efficiently generate bit streams for various resolutions. However, SVC requires more complex computation and higher memory bandwidth than H.264/AVC. In this paper, the performance and memory bandwidth requirement for a 3-spatial layer SVC hardware encoder is analyzed. Based on this analysis, a novel hardware architecture for memory bandwidth reduction for source data and inter-layer data access is proposed. Furthermore, the memory access latency of source data for the Base Layer is reduced by overlapping data load for the Base Layer with the execution of the Enhancement Layer. The analysis shows that the proposed hardware reduces the memory access by 75% achieving the encoding speed of 30 fps for a Full HD video at the operating clock frequency at 166 MHz. Simulation results show that the proposed hardware decreases BD-PSNR only by 0.042 dB and increases BD-BR only by 1.058%. © 2011 IEEE.
- KSP Keywords
- 6 MHz, Access Latency, Base layer, Clock frequency, Complex Computation, Data Access, Inter-layer, Memory Access, Scalable Video Coding, Spatial Scalability, bandwidth requirements