상세정보
학술대회
3D SiP Module Using TSV and Novel Low-Volume Solder-on-Pad(SoP) Process
- 발행일
- 201209
- 출처
- Electronic System-Integration Technology Conference (ESTC) 2012, pp.1-4
- 협약과제
- 12MB1600, 웨이퍼레벨 3차원 IC 설계 및 집적기술, 최광성
- 초록
- In this paper, a three-dimensional system in packaging (3D SiP) module in which a bottom interposer and a top interposer are interconnected vertically with the low-volume solder-on-pad (SoP) and through-silicon vias (TSVs) has been presented. A novel solder bumping material has been developed for the low-volume SoP and the thickness of SoP was measured about 10 μm. The low-volume SoP was evaluated by the cross-sectional photographs and the measurement of dc resistance using daisy-chain patterns. 3D SiP module composed of a GPU and two SRAM on the interposers were fabricated with this bumping material, a fluxless underfill and the vertical interconnection processes.
- KSP 제안 키워드
- 3D SiP, Cross-sectional, DC Resistance, Solder bumping, Three dimensional(3D), Through silicon vias(TSV), Vertical interconnection, low-volume, three-dimensional system