상세정보
학술지
Influence of Gate Dielectric/Channel Interface Engineering on the Stability of Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors
- 발행일
- 201405
- 출처
- Physica Status Solidi (A), v.211 no.9, pp.2126-2133
- ISSN
- 1862-6300
- 출판사
- Wiley-VCH Verlag GmbH
- 초록
- We report the simultaneous improvements of the threshold voltage (Vth) stabilities under the prolonged positive gate bias stress (PBS) and negative gate bias under illumination stress (NBIS) by employing the gate dielectric/channel interface engineering in the bottom-gate, DC-sputtered amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT). In the interfacial region, a-IGZO is grown under the low oxygen partial pressure (PO2) condition to minimize the damage from highly energetic oxygen anion bombardment into the substrate during sputtering. Meanwhile, high PO2 is employed during the bulk growth of active film to reduce the oxygen vacancy (VO) related defects in a-IGZO, which is known to be a main cause for the degradation of the electrical properties of TFT under NBIS. Owing to the lower damage of the gate dielectric by interface engineering during sputter deposition, the charge trapping or injection probability into the gate dielectric is diminished. Consequently, Vth instabilities due to both the electron trapping under PBS and the trapping of positively charged species under NBIS are alleviated simultaneously.
- KSP 제안 키워드
- Bottom gate, Bulk growth, Charge trapping, Charged species, Energetic oxygen, Gate bias stress, Low oxygen, Oxygen vacancies, Positively charged, Thin-Film Transistor(TFT), Zinc oxide(ZnO)