Subjects : All-digital phase-locked loop (ADPLL)
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Journal | 2011 | Low power digital PLL based TDC using low rate clocks Park Mijeong Electronics Letters, v.47, no.14, pp.793-794 | 1 | 원문 |
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| Type | Year | Research Project | Primary Investigator | Download |
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